1. Field of the Invention
The inventive concept relates to a semiconductor memory device, and more particularly, to a full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM) device having a layout in which the cell size can be readily reduced
2. Description of the Related Art
Of the semiconductor memory devices, SRAMs have characteristics such as low power consumption and fast response time when compared to dynamic random access memories (DRAMs), and are widely used in cache memory devices or mobile electronic products. Unit memory cells of an SRAM are classified as SRAM cells that use high value resistors as load devices and CMOS SRAM cells that use PMOS transistors as load devices. Also, the unit memory cells of the SRAM are classified as thin film transistor SRAM cells that use thin film transistors as load devices and bulk CMOS SRAM cells that use bulk transistors as load devices.
A bulk CMOS SRAM cell includes a pair of driving transistors, a pair of load transistors, and a pair of transmission transistors. The pair of driving transistors and the pair of transmission transistors are NMOS transistors and the pair of load transistors includes PMOS transistors. The bulk CMOS SRAM cell has high cell stability, but it has a low degree of integration and poor latch-up immunity due to a large cell size, since source and drain regions of the six transistors and channel regions of the six transistors are arranged in a plane on a substrate.
In a stack-type SRAM, the three pairs of transistors are stacked on layers different from each other to increase integration. In the stack-type SRAM, word lines, which are arranged on the uppermost layer and are connected to transistors, are arranged in a zigzag shape having a slant line, and thus, there is a limit to an ability to reduce cell size. Also, due to the slant line of the word lines, an align margin between neighboring bit line contact nodes is narrow and the current distribution of the transistors is not uniform. The align margin between the word lines and the bit line contact nodes is further reduced with the increase in integration. Accordingly, it is further difficult to perform a photographic process with respect to the word lines, and thus, the cell size cannot be readily reduced.